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Preliminary
Features
IBM0418A81QLAB IBM0436A81QLAB IBM0418A41QLAB IBM0436A41QLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
* 256K x 36 or 512K x 18 organizations * 128K x 36 or 256K x 18 organizations * 0.25 Micron CMOS technology * Synchronous Pipeline Mode of Operation with Self-Timed Late Write * Single Differential Extended HSTL Clock * +3.3V Power Supply, Ground, 1.5V VDDQ, and 0.75V VREF * HSTL Input AND Outputs.. * Registered Addresses, Write Enables, Synchronous Select, and Data Ins.
* Registered Outputs * Common I/O * Asynchronous Output Enable and Power Down Inputs * Boundary Scan using limited set of JTAG 1149.1 functions * Byte Write Capability and Global Write Enable * 7 x 17 Bump Ball Grid Array Package with SRAM JEDEC Standard Pinout and Boundary SCAN Order * Programmable Impedance Output Drivers
Description
The 4Mb and 8Mb SRAMs--IBM0436A41QLAB, IBM0418A41QLAB, IBM0418A81QLAB, and IBM0436A81QLAB--are Synchronous Pipeline Mode, high-performance CMOS Static Random Access Memories that are versatile, have wide I/O, and can achieve 3ns cycle times. Differential K clocks are used to initiate the read/write operation and all internal operations are self-timed. At the rising edge of the K clock, all Addresses, WriteEnables, Sync Select, and Data Ins are registered internally. Data Outs are updated from output registers off the next rising edge of the K clock. An internal Write buffer allows write data to follow one cycle after addresses and controls. The chip is operated with a single +3.3V power supply and is compatible with HSTL I/O interfaces.
trrh3316. 01 11/98
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
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IBM0418A81QLAB IBM0436A81QLAB IBM0418A41QLAB IBM0436A41QLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
x36 BGA Pinout (Top View)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQ19 DQ22 VDDQ DQ24 DQ25 VDDQ DQ34 DQ33 VDDQ DQ31 DQ28 NC NC VDDQ 2 SA NC SA DQ18 DQ20 DQ21 DQ23 DQ26 VDD DQ35 DQ32 DQ30 DQ29 DQ27 SA NC TMS 3 SA SA SA VSS VSS VSS SBWc VSS VREF VSS SBWd VSS VSS VSS M1* SA TDI 4 NC NC VDD ZQ SS G NC NC VDD K K SW SA SA VDD SA TCK 5 SA SA SA VSS VSS VSS SBWb VSS VREF VSS SBWa VSS VSS VSS M2* SA TDO 6 SA NC,SA(8Mb) SA DQ9 DQ11 DQ12 DQ14 DQ17 VDD DQ8 DQ5 DQ3 DQ2 DQ0 SA NC NC 7 VDDQ NC NC DQ10 DQb13 VDDQ DQb15 DQb16 VDDQ DQ7 DQ6 VDDQ DQ4 DQ1 NC ZZ VDDQ
Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD respectively.
x18 BGA Pinout (Top View)
1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQ14 NC VDDQ NC DQ17 VDDQ NC DQ12 VDDQ DQ11 NC NC NC VDDQ 2 SA NC SA NC DQ15 NC DQ16 NC VDD DQ13 NC DQ10 NC DQ9 SA SA TMS 3 SA SA SA VSS VSS VSS SBWb VSS VREF VSS NC VSS VSS VSS M1 SA TDI 4 NC NC VDD ZQ SS G NC NC VDD K K SW SA SA VDD NC TCK 5 SA SA SA VSS VSS VSS NC VSS VREF VSS SBWa VSS VSS VSS M2 SA TDO 6 SA NC,SA(8Mb) SA DQ0 NC DQ2 NC DQ4 VDD NC DQ7 NC DQ6 NC SA SA NC 7 VDDQ NC NC NC DQ1 VDDQ DQ3 NC VDDQ DQ8 NC VDDQ NC DQ5 NC ZZ VDDQ
Note: * M1 and M2 are clock mode pins. For this application, M1 and M2 need to connect to VSS and VDD respectively.
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
trrh3316.01 11/98
Page 4 of 6
Preliminary
IBM0418A81QLAB IBM0436A81QLAB IBM0418A41QLAB IBM0436A41QLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Pin Description
Address Input SA0-SA18 for 512Kx18 SA0-SA17 for 256Kx36 SA0-SA17 for 256Kx18 SA0-SA16 for 128Kx36 Data I/O DQ0-DQ17 for 512Kx18 DQ0-DQ35 for 256Kx36 Differential Input Register Clocks Write Enable, Global Write Enable, Byte a (DQ0-DQ8) Write Enable, Byte b (DQ9-DQ17) Write Enable, Byte c (DQ18-DQ26) Write Enable, Byte d (DQ27-DQ35) IEEE 1149.1 Test Inputs (LVTTL levels) IEEE 1149.1 Test Output (LVTTL level)
SA0-SA18
G
Asynchronous Output Enable
DQ0-DQ35
SS
Synchronous Select
K, K SW SBWa SBWb SBWc SBWd TMS,TDI,TCK TDO
M1, M2 VREF(2) VDD VSS VDDQ ZZ ZQ NC
Clock Mode Inputs- Selects Single or Dual Clock Operation. HSTL Input Reference Voltage Power Supply (+3.3V) Ground Output Power Supply Asynchronous Sleep Mode Output Driver Impedance Control No Connect
Ordering Information
Part Number IBM0418A41QLAB - 3 IBM0418A41QLAB - 4 IBM0418A41QLAB - 5 IBM0436A41QLAB - 3 IBM0436A41QLAB - 4 IBM0436A41QLAB - 5 IBM0418A81QLAB - 3 IBM0418A81QLAB - 4 IBM0418A81QLAB - 5 IBM0436A81QLAB -3 IBM0436A81QLAB -4 IBM0436A81QLAB -5 Organization 256K x 18 256K x 18 256K x 18 128K x 36 128K x 36 128K x 36 512K x 18 512K x 18 512K x 18 256K x 36 256K x 36 256K x 36 Speed 1.7ns Access / 3.0ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle 1.7ns Access / 3.0ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle 1.7ns Access / 3.0ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle 1.7ns Access / 3.0ns Cycle 2.0ns Access / 4.0ns Cycle 2.25ns Access /5.0ns Cycle Leads 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA 7 x 17 BGA
trrh3316. 01 11/98
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
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IBM0418A81QLAB IBM0436A81QLAB IBM0418A41QLAB IBM0436A41QLAB 8Mb (256Kx36 & 512x18) and 4Mb (128Kx36 & 256Kx18) SRAM
Preliminary
Revision Log
Revision 9/98 11/98 Initial Release Changed part numbers from Rev A to B. Input levels adjusted. Contents of Modification
For a complete datasheet, please contact your IBM sales representative.
(c)IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document.
trrh3316.01 11/98
Page 6 of 6
(R)
(c) International Business Machines Corp.1998
Copyright
Printed in the United States of America All rights reserved
IBM and the IBM logo are registered trademarks of the IBM Corporation.
This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT.
For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at http://www.chips.ibm.com
IBM Microelectronics manufacturing is ISO 9000 compliant.
GA14-4662-00

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